The present invention relates to a fuse latch for a memory circuit, and more particularly to multiplexer employed within the fuse latch having a reduced size and reduced current consumption.
In manufacturing high volume, low margin products, like memory chips, manufacturing cost and performance of the products are important factors to be considered. There have been efforts in the manufacturing industry of memory chips to reduce the manufacturing cost of memory chips, while maintaining or improving their performance. One of the factors determining the manufacturing cost is a size of a memory chip, that is, typically, the smaller a size of a memory chip, the lower the manufacturing cost of the memory chip.
One of the components having an effect on a size of a memory chip is fuse latches in the memory chip. Generally, a memory chip has a significant number of fuse latches. For example, there are about 30,000 fuse latches in a typical memory chip of 1 G-bit SDRAM (synchronous dynamic random access memory). Thus, a size of the fuse latch is one factor in determining the size of a memory chip.
Referring to FIG. 1, a conventional fuse latch is illustrated for a memory circuit. A conventional fuse latch has a complementary metal oxide semiconductor (CMOS) multiplexer receiving input address data ADD and ADDxe2x80x2 and a latch control signal CONT. The input address data ADD and ADDxe2x80x2 have a certain level (i.e., CMOS level) of voltage, and the latch control signal CONT is dependent on a status of a (not shown) of the fuse latch.The CMOS multiplexer 10 includes, for example, a first CMOS transistor 12 and a second CMOS transistor 14. The CMOS multiplexer 10 also has a latch input terminal 16 through which the control signal CONT is provided to the first and second CMOS transistors 12 and 14, and a latch output terminal 18 for generating a multiplexed signal to a decoder 19. The first CMOS transistor 12 receives true address data ADD and the second CMOS transistor 14 receives complement address data ADDxe2x80x2. The control signal CONT is provided to the first CMOS transistor 12 through an inverter 17 and to the second CMOS transistor 14 to enable/disable the first and second CMOS transistors 12 and 14 depending on the status of the fuse. The CMOS multiplexer 10 multiplexes the true and the complement address data ADD and ADDxe2x80x2 in response to the control signal CONT. In other words, depending on whether the fuse has been blown or is intact, either true address data ADD or complement address data ADDxe2x80x2 propagates through the CMOS multiplexer 10 to the decoder 19.
Referring to FIG. 2, a cross-sectional view of a typical CMOS transistor used in a conventional fuse latch in FIG. 1 is illustrated. A typical CMOS transistor 20 has a serial combination of a p-channel transistor 22 and an n-channel transistor 24. A typical CMOS transistor 20 uses a dopant which is diffused into the surface of substrate 26 to form, for example, an n-well 28 as well as drain and source regions of the p-channel transistor 22 and the n-channel transistor 24. Since the diffusion of the dopant occupies some space to form the n-well 28, the p-channel transistor 22 is larger than the n-channel transistor 24. In a conventional fuse latch (referring to FIG. 1), the size of p-channel transistors is, for example, nearly twice the size of n-channel transistors. Thus, a CMOS multiplexer including the p-channel transistors contributes to an increase in the size of a conventional fuse latch, or a memory chip.
Accordingly, a need exists for a fuse latch having a reduced size, thereby reducing the size of a memory chip.
The present invention relates to a fuse latch circuit having a reduced size and a reduced current consumption. A fuse latch of the present invention includes a plurality of address lines, an input terminal for receiving a control signal varying dependent on status of a fuse, a multiplexer having single type transistors for multiplexing the plurality of address lines in response to the control signal, and an output terminal for providing a multiplexed signal from the multiplexer to a decoder. All the transistors of the multiplexer may be either only n-channel metal oxide semiconductor (NMOS) transistors or only p-channel metal oxide semiconductor (PMOS) transistors. The decoder may be a dynamic decoder for eliminating a voltage drop due to threshold voltages of the transistors. In case of NMOS transistors, the dynamic decoder may include an NMOS logic circuit having a NMOS transistor enabled in response to the multiplexed signal from the multiplexer. In case of PMOS transistors, the dynamic decoder may include a PMOS logic circuit having a PMOS transistor enabled in response to the multiplexed signal.
The plurality of address lines may be applied with address signals with a voltage lower than a source voltage of the decoder. The address lines may include, for example, a first address line for providing true address data and a second address line for providing complement address data. The multiplexer may have, for example, a first transistor for receiving the true address data and a second transistor for receiving the complement address data. The first and second transistors may be enabled or disabled in response to the control signal, and share either a drain region or a source region.
For eliminating the voltage drop, the fuse latch may include a voltage supply unit for providing a boost voltage to the first and the second transistors. The voltage supply unit may be connected to a wordline boost voltage supply for a wordline driver, where the fuse latch is used for a decoupling capacitance of the wordline boost voltage. The boost voltage may be equal to or higher than a source voltage provided to the decoder, preferably, is equal to a sum of the source voltage provided to the decoder and a threshold voltage of the transistors in the multiplexer. The fuse latch may further include a first inverter for inverting the control signal and a second inverter for inverting an output signal of the first inverter and for providing an inverted signal to the input terminal. The first inverter may be coupled between the input terminal and the first transistor and may receive the boost voltage from the voltage supply unit. The second inverter may be coupled between the output of the first inverter and the input terminal and also receive the boost voltage from the voltage supply unit.
The size of a multiplexer having single type transistors, preferably only n-channel transistors, may be substantially smaller than that of a conventional multiplexer having CMOS transistors. The multiplexer may include only NMOS transistors which also reduces the current consumption.